1. Field of the Invention
The present invention relates to a reduction method of power consumption in a semiconductor storage device, and more particularly relates the low power consumption method of a semiconductor storage memory to reduce the load capacity of a bit line to reduce power consumption, by cutting off the bit line on the boundary, for example, between a data or program storage area and a standby storage area, for example, in read-only memory.
2. Description of the Related Art
Generally, a plurality of pieces of read-only memory (ROM) is mounted on a semiconductor integrated circuit. FIG. 1 shows such a conventional semiconductor integrated circuit. In FIG. 1, two central processing units (CPU) 11 and 12 are mounted on a semiconductor integrated circuit 10. For example, dedicated ROM 13 and 14 are mounted on the CPU 11 and 12, respectively. For example, programming data is stored in such ROM as data. If it is scheduled that such data is updated in or added to such a semiconductor integrated circuit in a design stage, the number of words of the ROM as a programming area is designed larger than actually used from the beginning, expecting such a data modification.
When a program bug is discovered or the program is rewritten in a new program later, sometimes an area greatly exceeding the initially designed programming area must be needed depending on its modification contents. In that case, in order to greatly increase the number of words of the ROM and re-design the semiconductor integrated circuit accordingly, a mask and a reticle must be newly prepared for all layers, which becomes a big problem in terms of a cost and a turnaround time. In order to avoid such a problem, as shown in FIG. 1, a fairly large standby area compared to the initial programming area is generally prepared as the memory space of the ROM and designed.
FIG. 2 shows the memory space of read-only memory shown in FIG. 1. In FIG. 2, a programming area is constituted by word lines WL0 up to WLn, and a standby area is constituted by word lines WLn+1 up to WLn+m. Each word line is connected to the gate of a transistor corresponding to the memory cell, and one terminal of the transistor is connected to a power voltage Vss.
In the programming area, some of the other terminal of the transistor is connected to the bit line and some is not connected to it. The connected ones are indicated by a black circle at the intersection with a bit line, and unconnected ones are indicated a white circle. In the standby area, no other terminal of the transistor is connected to a bit line. The existence/non-existence of connection with the bit line corresponds to, for example, “1” and “0” of data stored in the ROM, and by modifying this connection state, programming data can be modified. Since this modification corresponds to the existence/non-existence of a contact layer (beer) on each transistor, for example, by preparing a new reticle for a contact layer, the programming data can be updated.
However, in the conventional semiconductor integrated circuit shown in FIGS. 1 and 2, since a large space including the standby area is secured as a ROM memory space, the length of the bit line is unnecessarily extended, the pre-charge/discharge current of the bit line increases accordingly. This pre-charge/discharge current of the bit line occupies most of the ROM power consumption while power needed by such a longer bit line has no relation with the operation of the semiconductor integrated circuit. Therefore, the increase of the consumption power of the semiconductor integrated circuit due to such power is a problem.
As the prior art concerning an semiconductor storage device, such as ROM or the like, Patent reference 1 discloses a semiconductor storage device capable of reducing its chip area without increase in the number of manufacturing processes, by sharing a main memory cell array and a redundant memory cell array with one column decoder.
Patent reference 2 discloses a non-volatile semiconductor storage device capable of preventing the excess erase of an unused memory cell and a mis-operation due to bit line leak, by not applying erase bias to a replaced memory cell array.
Patent reference 1: Japanese Patent Application Publication No. H9-162308 “Semiconductor Storage Device”
Patent reference 2: Japanese Patent Application Publication No. 2002-150790 “Non-volatile Semiconductor Storage Device”
However, if a standby area other than a programming area is provided in read-only memory when such a prior art is used, the increase of ROM power consumption cannot be prevented.